I believe the first cores in chisel which is a Haskell/ML type HDL, so SAIL fits right in.
Just because people are used to other ways of doing things doesn’t make those ways better. “I don’t want to learn something new“ certainly isn’t a compelling argument.
Learning new things is good. This should be encouraged. But going from SystemVerilog to Chisel is not a small step. It's not really a question of what's better or worse. It's a paradigm shift in the way you think about how a design is captured and expressed. It's not like learning how to use a new dishwasher or driving a new car. It's learning a new stack of tools and flows. All under the pressure of delivering a new product on spec, on time and on budget. For many teams running in a tight cycle of design->tape out, it is not realistic to ask them to "learn something new".
When you change the context, the perception changes. If you're a grad student who has chosen to dive head first into Chisel after already mastering functional programming and want to get more into hardware design, that's a different story.
Just because people are used to other ways of doing things doesn’t make those ways better. “I don’t want to learn something new“ certainly isn’t a compelling argument.